In a receiving terminal of a serial communication system, a clock and data recovery circuit (CDR) is used to extract a clock and recovery data from the received serial data stream, and performance of the CDR directly restricts communication quality. A phase interpolator (PI) is used to adjust a clock phase sampled in the CDR to realize correct sampling of data. The PI capable of accurately adjusting the clock phase is very important for a case that data from a transmitting terminal can be recovered correctly at the receiving terminal.
In an actual application, a sampling clock edge resulted from a sudden phase jump may occur in an operation process of the CDR due to phase drift of the transmitting clock, environment temperature change, or power supply voltage variation, which reduces jitter performance, and directly deteriorates dynamic performance of the CDR.